As is well known, charge pump circuits are widely used in many electronic devices to obtain voltage values higher than a supply reference by using capacitors as charge storage elements. A classic charge pump circuit normally comprises four capacitors suitably connected to four enable signals, or phases, of the charge pump circuit.
A four-phase charge pump circuit is able to operate in a range of frequencies equal to 10-50 MHz. However, this range is insufficient for some applications.
Charge pump latch circuits are known to be able to output signals at rather high frequencies (e.g., 100 MHz and more), with respect to the traditional four-phase charge pump circuits which reach their maximum at 50 Mhz. This is possible since the charge pump latch circuits operate with only two phases and only use low voltage transistors.
A conventional charge pump circuit of the latch type is shown in FIG. 1. The charge pump latch circuit 1 has an input terminal IN connected to a first voltage reference (in particular the supply voltage Vdd), and an output terminal OUT connected to a load, which is illustrated by the parallel of a load capacitor CL and a load current generator IL inserted between this output terminal OUT and a second voltage reference (in particular the ground GND).
The charge pump latch circuit 1 comprises a plurality of N charge pump stages CB1-CBN inserted in cascade between the input IN and output OUT terminals and connected to a first enable terminal FX and to a second enable terminal FN supplying respective first and second enable signals, or phases (which for the sake of simplicity likewise are indicated with the references FX and FN). In particular, the enable signals, or phases, FX and FN are complementary to each other.
The charge pump latch circuit 1 is thus a two-phase circuit, able to operate at rather high frequencies (e.g., 100 MHz and more), due to the presence of suitable latch circuits L1-LN inserted in each charge pump stage CB1-CBN.
In more detail, each charge pump stage CBN comprises at least one first pump capacitor CUp and one second pump capacitor CDown inserted between the first enable terminal FX and a first inner circuit node Up and between the second enable terminal FN and a second inner circuit node Down, respectively.
Each charge pump stage CBN also comprises a respective latch circuit LN that is inserted between the first inner circuit node Up and the second inner circuit node Down and that comprises Low Voltage (or LV) transistors. In particular, each latch circuit LN comprises at least one pair of N-channel MOS transistors and a pair of P-channel MOS transistors, suitably connected to form opposite pairs of CMOS switches having control terminals or gates connected to the enable terminals FX and FN, for the alternating connection (and the relative charge sharing) of the pump capacitors CUp and CDown.
Since the charge pump stages CB1-CBN are placed in parallel, in the operation of the latch circuit 1 consecutive stages work in phase opposition with each other and the enable signals, or phases, FX and FN are at any time complementary to each other.
It is interesting to note that the voltage value VInt on an intermediate circuit node INT between two consecutive charge pump stages is kept practically constant during the whole clock period. Moreover, the widening of the range of operation frequencies allows a reduction in the sizes of the charge pump capacitors CUp and CDown and thus of the area occupied by the latch circuit 1 as a whole.
However, while the use of these charge pump capacitors CUp and CDown for the turn-on and the turn-off of the transistors of the latch circuit 1 allows there to be obtained a remarkable circuit simplification for the latch circuit itself, on the other hand they constitute a limit in the supply of current to the circuit, in particular when the supply voltage Vdd becomes close to the threshold voltage of the transistors in the latch circuit 1 or when the same is requested to supply a greater and greater current value.
In general, charge pump latch circuits do not operate very well at very low supply voltages. It is in fact possible to verify that, when the supply voltage Vdd decreases, a charge pump latch circuit of the type shown in FIG. 1 does not succeed in supplying a sufficient load current IL.
To overcome this limit, a charge pump latch circuit has been provided with a stabilization circuit connected to the enable terminals FX and FN in order to ensure a correct biasing of the transistors during the charge sharing periods.
For example, one solution described in European Patent Application No. 06 425497.2 of the same Assignee proposes the use of supplementary capacities only when the supply voltage becomes close to the threshold voltage of the transistors or when the charge pump latch circuit is requested to supply a greater and greater current. These supplementary capacities, by biasing the gate terminals of the pass transistors, allow the correct turn-on and turn-off of the same up to the end of the charge sharing.
This solution, even though it is able to operate with supply voltages lower than 1V, loses the typical characteristic of the charge pump latch circuits, i.e., the capacity of turning on and off the pass transistors slowly so as to avoid stressing the thin oxide layers whereon the gate areas of such transistors are realized.
Moreover, during switches at high frequency some asymmetries occur in the biasing voltages of the pass transistors between the upper and the lower circuit portion of the latch circuit.
These two drawbacks could cause stress on the oxides and an improper operation of the charge pump latch circuit, so as not to allow the meeting of the current and voltage requirements.
FIG. 2 shows a view of the charge pump latch circuit described in European Patent Application No. 06 425497.2. In this circuit, the phases FX and FN are, at any time, complementary to each other.
There are two different equivalent conditions as follows.
1) FN=Vdd, FX=0, VcD(i-1) is brought high, VcU(i-1) is brought low, VcD(i) is low while VcUpi is high. In this case the node PgU is brought high (at Vi) while the node PgD is bought low (by a Vdd with respect to a Vi), thus allowing the turning on of the transistor MpD and the turning off the transistor MpU. In the same semi-period the node NgD is brought high (by a Vdd with respect to Vi) and the node NgU is brought low. Thus the transistor MnD is turned on, while the transistor MnU is turned off. In this way, the charge pump latch circuit of FIG. 2 allows there to be obtained the charge sharing between the two adjacent bottom capacities, connected to the nodes VcD(i−1) and VcD(i), while it is forbidden between the two upper capacities, connected to the nodes VcU(i−1) and Vcu(i).
2) FN=0, FX=Vdd. In this case the latch circuit of FIG. 2 operates in a similar way to the previous situation. However, this time the charge sharing occurs between the two upper capacities, connected to the nodes VcU(i−1) and VcU(i).
It is to be noted that during the two semi-periods in which the nodes PgD, PgU, NgD, NgU, go high or low, they always remain constant for the whole time of the sharing, and at such a voltage as to allow an efficient turn-on and turn-off of the pass transistors connected thereto, also when the supply voltage Vdd is equal to 1V, as shown in FIG. 3. In particular, FIG. 3 shows the semi-period in which the charge sharing occurs between the two bottom capacities, i.e., the capacities connected to the nodes VcD(i−1) and VcD(i).
The transistors Mp1, Mp2, Mn1, and Mn2 allow the capacities Cb to update at the voltage they refer to and to recover that charge lost to drive the pass transistors.
To completely evaluate the characteristics of this circuit, we will evaluate the differences of potential between the various nodes. First, consider the voltage differences between the nodes of a generic stage j of the single charge pump latch circuit, as shown in FIG. 4 or equivalently of one of the charge pump stages of the circuit shown in FIG. 2.
Starting from the most intuitive condition, which is that of end sharing (“End Sharing” instant—FIG. 4), when the voltage difference between the nodes A and B is obviously void:
      V          AB              End        ⁢        _        ⁢        Sh              =  0During the sharing, the voltage at the node A has been reduced by ΔV, being:
      Δ    ⁢                  ⁢    V    =                    I        L            ⁢      T        C  while that at the node B increases by the same amount, thus at the beginning of the sharing there occurs:
      V          AB              Start        ⁢        _        ⁢        Sh              =      2    ⁢    Δ    ⁢                  ⁢    V  
But going back to the end sharing instant, at this point the phases switch (“Start No Sharing” instant) and, in consequence, the voltage at the node A decreases by a value equal to the supply voltage Vdd, while that at the node B increases by the same amount. This implies:
      V          AB              Start        ⁢        _        ⁢        NoSh              =      2    ⁢    Vdd  
During this semi-period there is no sharing in the stage j, while it is present in the adjacent stages, thus the capacity at the node A receives charge from that of the previous stage and the capacity at the node B transfer charge to that of the successive stage. At the end of the semi-period (“End No Sharing” instant) the voltage at the node A has increased by ΔV while that at the node B has been reduced by ΔV, thus there occurs:
      V          AB              Endt        ⁢        _        ⁢        NoSh              =            2      ⁢      Vdd        -          2      ⁢      Δ      ⁢                          ⁢      V      
The results so far obtained are summarized in the following table.
TABLE 1      V          AB              End        ⁢        _        ⁢        Sh              =  0End sharing between A and B       V          AB              Start        ⁢        _        ⁢        NoSh              =      2    ⁢    Vdd  Start no sharing between A and B       V          AB              Endt        ⁢        _        ⁢        NoSh              =            2      ⁢      Vdd        -          2      ⁢      ΔV      End no sharing between A and B       V          AB              Start        ⁢        _        ⁢        Sh              =      2    ⁢    ΔV  Start sharing between A and B
Now we will reconsider a double charge pump circuit, making reference to the schemes of FIGS. 5 and 6. In particular, the circuit comprises two upper nodes A and B and two lower nodes C and D whereto respective capacities are connected. It is verified that the potential differences between the nodes during the operation are the following ones.
1) under the Start Sharing Up and Start No Sharing Down conditions of FIG. 5:VBA=2ΔV; VCA=Vdd+ΔV; VCD=2Vdd; VDB=−(Vdd+ΔV)
2) under the End Sharing Up and End No Sharing Down conditions of FIG. 6:VBA=0; VCA=Vdd−ΔV; VCD=2Vdd−2ΔV; VDB=−(Vdd−ΔV)
Considering then the circuit complete with the switches as shown in FIG. 2, the absolute values of the voltages at the nodes at the end of the semi-period in which the charge sharing has occurred between the two bottom capacities are summarized in the following table.
TABLE 2VCUi-1Vi − Vdd + ΔVVCDi-1ViVCUiVi + Vdd − ΔVVCDiViPgDVi − VddPgUViNgDVi + VddNgUVi
Therefore, observing the differences of potential, the two pass transistors MpD and MnD on the bottom of FIG. 2 are on while those MpU and MnU on the top are off. Given the difficulty of obtaining perfectly crossed phases of the charge pump circuit, they are preferably realized overlapped or disoverlapped. In fact, when the phases are overlapped (i.e., when both FX and FN are equal to Vdd), the values of the voltages at the nodes become the following.
TABLE 3VCUi-1Vi + ΔVVCDi-1ViVCUiVi + Vdd − ΔVVCDiVi + VddPgDViPgUViNgDVi + VddNgUVi + Vdd
It results that the pass transistor MpU is on, but also that the transistors Mn1 and Mn2 are on. In consequence, the capacities Cb which drive the N-channel MOS transistors are unloaded on the pumping capacity C and in a different way with respect to each other. This creates an asymmetry of the potentials at the nodes between the high part of the charge pump circuit and the low part during the charge sharing phases, as graphically shown in FIG. 7.